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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos single +5 v supply, low power, 12-bit sampling adc ad7880 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram + r r sampling comparator control logic sar + counter clkin cs convst rd busy mode v dd low power control circuit v ina v inb v ref agnd dgnd db0 db11 12-bit dac ad7880 three state buffers features 12-bit monolithic a/d converter 66 khz throughput rate 12 m s conversion time 3 m s on-chip track/hold amplifier low power power save mode: 2 mw typ normal operation: 25 mw typ 70 db snr fast data access time: 57 ns small 24-lead soic and 0.3" dip packages applications battery powered portable systems digital signal processing speech recognition and synthesis high speed modems control and instrumentation general description the ad7880 is a high speed, low power, 12-bit a/d converter which operates from a single +5 v supply. it consists of a 3 m s track/hold amplifier, a 12 m s successive-approximation adc, versatile interface logic and a multiple-input-range circuit. the part also includes a power save feature. an internal resistor network allows the part to accept both uni- polar and bipolar input signals while operating from a single +5 v supply. fast bus access times and standard control inputs ensure easy interfacing to modern microprocessors and digital signal processors. the ad7880 features a total throughput time of 15 m s and can convert full power signals up to 33 khz with a sampling fre- quency of 66 khz. in addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the ad7880 is also fully specified for dynamic performance parameters including har- monic distortion and signal-to-noise ratio. the ad7880 is fabricated in analog devices linear compat- ible cmos (lc 2 mos) process, a mixed technology process that combines precision bipolar circuits with low power cmos logic. the part is available in a 24-pin, 0.3 inch-wide, plastic or hermetic dual-in-line package (dip) as well as a small 24-lead soic package. product highlights 1. fast conversion time. 12 m s conversion time and 3 m s acquisition time allow for large input signal bandwidth. this performance is ideally suited for applications in areas such as telecommunications, audio, sonar and radar signal processing. 2. low power consumption. 2 mw power consumption in the power-down mode makes the part ideally suited for portable, hand held, battery pow- ered applications. 3. multiple input ranges. the part features three user-determined input ranges, 0 v to +5 v, 0 v to 10 v and 5 v. these unipolar and bipolar ranges are achieved with a 5 v only power supply.
rev. 0 C2C ad7880Cspecifications parameter b versions 1 c versions 1 units test conditions/comments dynamic performance 2 signal-to-noise ratio 3 (snr) 70 70 db min typically snr is 72 db v in = 1 khz sine wave, f sample = 66 khz total harmonic distortion (thd) C80 C80 db typ v in = 1 khz sine wave, f sample = 66 khz peak harmonic or spurious noise C80 C80 db typ v in = 1 khz, f sample = 66 khz intermodulation distortion (imd) second order terms C80 C80 db typ fa = 0.983 khz, fb = 1.05 khz, f sample = 66 khz third order terms C80 C80 db typ fa = 0.983 khz, fb = 1.05 khz, f sample = 66 khz dc accuracy resolution 12 12 bits all dc accuracy specifications apply for the three analog input ranges integral nonlinearity 1 1 lsb max differential nonlinearity 1 1 lsb max guaranteed monotonic full-scale error 15 5 lsb max bipolar zero error 10 5 lsb max unipolar offset error 5 5 lsb max analog input input voltage ranges 0 to v ref 0 to v ref volts see figure 5 0 to 2 v ref 0 to 2 v ref volts see figure 6 v ref v ref volts see figure 7 input resistance 10 10 m w min 0 to v ref range 5/12 5/12 k w min/max 8 k w typical: 0 to 2 v ref range 5/12 5/12 k w min/max 8 k w typical: v ref range reference input v ref (for specified performance) 5 5 v 5%: normally v ref = v dd (see reference input section) i ref 1.5 1.5 ma max nominal reference range 2.5/v dd 2.5/v dd v min/max see figure 3 for degradation in performance down to 2.5 v logic inputs convst , rd , cs , clkin input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current, i in 10 10 m a max v in = 0 v or v dd input capacitance, c in 4 10 10 pf max mode input input high voltage, v inh 4 4 v min input low voltage, v inl 1 1 v max input current, i in 125 125 m a max v in = 0 v or v dd input capacitance, c in 4 10 10 pf max logic outputs db11Cdb0, busy output high voltage, v oh 4.0 4.0 v min i source = 400 m a output low voltage, v ol 0.4 0.4 v max i sink = 1.6 ma db11Cdb0 floating-state leakage current 10 10 m a max floating-state output capacitance 4 10 10 pf max conversion conversion time 12 12 m s max f clkin = 2.5 mhz track/hold acquisition time 3 3 m s max power requirements v dd +5 +5 v nom 5% for specified performance i dd normal power mode @ +25 c 7.5 7.5 ma max typically 4 ma; mode = v dd t min to t max 10 10 ma max typically 5 ma; mode = v dd power save mode @ +25 c 750 750 m a max logic inputs @ 0 v or v dd ; mode = 0 v t min to t max 1 1 ma max logic inputs @ 0 v or v dd ; mode = 0 v power dissipation normal power mode @ +25 c 37.5 37.5 mw max v dd = 5 v: typically 20 mw; mode = v dd t min to t max 50 50 mw max v dd = 5 v: typically 25 mw; mode = v dd power save mode @ +25 c 3.75 3.75 mw max v dd = 5 v: typically 2 mw; mode = 0 v t min to t max 5 5 mw max v dd = 5 v: typically 2.5 mw; mode = 0 v notes 1 temperature ranges are as follows: b/c versions, C40 c to +85 c. 2 v in = 0 to v ref 3 snr calculation includes distortion and noise components. 4 sample tested @ +25 c to ensure compliance. specifications subject to change without notice. (v dd = +5 v 6 5%, v ref = v dd , agnd = dgnd = o v, f clkin = 2.5 mhz, mode = v dd unless otherwise noted. all specifications t min to t max unless otherwise noted.)
ad7880 rev. 0 C3C timing characteristics 1 limit at +25 8 c limit at t min , t max parameter (all versions) (all versions) units conditions/comments t 1 50 50 ns min convst pulse width t 2 130 130 ns min convst to busy falling edge t 3 0 0 ns min busy to cs setup time t 4 0 0 ns min cs to rd setup time t 5 0 0 ns min cs to rd hold time t 6 60 75 ns min rd pulse width t 7 2 57 70 ns max data access time after rd t 8 3 55 ns min bus relinquish time after rd 50 50 ns max notes 1 timing specifications in bold print are 100% production tested. all other times are sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 t 7 is measured with the load circuit of figure 2 and defined as the time required for an output to cross 0.8 v or 2.4 v. 3 t 8 is derived from the measured time taken by the data outputs to change by 0.5 v when loaded with the circuit of figure 2. the measured number is then extrapo- lated back to remove the effects of charging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. (v dd = +5 v 6 5%, v ref = v dd , agnd = dgnd = 0 v) table i. truth table cs convst rd function 1 1 x not selected 1 j 1 start conversion g 0 1 0 enable adc data 0 1 1 data bus three stated absolute maximum ratings* v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v v ina , v inb to agnd (figure 5) . . . . . . C0.3 v to v dd + 0.3 v v ina to agnd (figure 6) . . . . . . . . . C0.6 v to 2 v dd + 0.6 v v ina to agnd (figure 7) . . . . . Cv dd C 0.3 v to v dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v to v dd digital inputs to dgnd . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital outputs to dgnd . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range industrial (b, c versions) . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . . 10 mw/ c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7880 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. db0 ?db11 data valid t 1 t convert t 2 t 3 t 4 t 5 t 6 t 7 t 8 convst busy cs rd three-state track/hold goes into hold figure 1. timing diagram to output pin 1.6ma 2.1v + 200? 50pf figure 2. load circuit for access and relinquish time
ad7880 C4C rev. 0 pin function description pin pin no. mnemonic function 1v ina analog input. 2v inb analog input. 3 agnd analog ground. 4v ref voltage reference input. this is normally tied to v dd . 5 cs chip select. active low logic input. the device is selected when this input is active. 6 convst convert start. a low to high transition on this input puts the track/hold into hold mode and starts con- version. this input is asynchronous to the clkin and is independent of cs and rd . 7 rd read. active low logic input. this input is used in conjunction with cs low to enable data outputs. 8 busy active low logic output. this status line indicates converter status. busy is low during conversion. 9 clkin clock input. ttl-compatible logic input. used as the clock source for the a/d converter. the mark/ space ratio of the clock can vary from 40/60 to 60/40. 10 dgnd digital ground. 11 . . . 22 db0Cdb11 three-state data outputs. these become active when cs and rd are brought low. 23 mode mode input. this input is used to put the device into the power save mode (mode = 0 v). during normal operation, the mode input will be a logic high (mode = v dd ). 24 v dd power supply. this is nominally +5 v. ordering guide bipolar full-scale zero temperature error error package model range (lsbs) (lsbs) option* ad7880bn C40 c to +85 c 15 10 n-24 ad7880bq C40 c to +85 c 15 10 q-24 ad7880cn C40 c to +85 c 5 5 n-24 ad7880cq C40 c to +85 c 5 5 q-24 ad7880br C40 c to +85 c 15 10 r-24 AD7880CR C40 c to +85 c 5 5 r-24 *n = plastic dip; q = cerdip; r = soic (small outline integrated circuit). pin configuration top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 23 22 21 20 19 18 17 16 15 ad7880 agnd clkin dgnd db0 db1 db2 db3 db4 db5 db6 v dd db8 v ina v inb db7 db9 db10 db11 mode cs convst rd busy v ref
ad7880 rev. 0 C5C + r v ina v inb r v dac figure 4. ad7880 input circuit the ad7880 accommodates three separate input ranges, 0 to v ref , 0 to 2 v ref and v ref . the input configurations corre- sponding to these ranges are shown in figures 5, 6 and 7. with v ref = v dd and using a nominal v dd of +5 v, the input ranges are 0 v to 5 v, 0 v to 10 v and +5 v, as shown in table ii. table ii. analog input ranges analog input input connections connection range v ref v ina v inb diagram 0 v to +5 v v dd v in v in figure 5 0 v to +10 v v dd v in agnd figure 6 5 v v dd v in v ref figure 7 + r r sampling comparator v ina v inb v ref agnd 12-bit dac 0 to v ref v ref = 0 to v ref v in figure 5. 0 to v ref unipolar input configuration + r r sampling comparator v ina v inb v ref agnd 12-bit dac 0 to v ref v ref = 0 to 2v ref v in figure 6. 0 to 2 v ref unipolar input configuration + r r sampling comparator v ina v inb v ref agnd 12-bit dac 0 to v ref v ref = v ref v in figure 7. v ref bipolar input configuration circuit information the ad7880 is a +5 v single supply 12-bit a/d converter. the part requires no external components apart from a 2.5 mhz ex- ternal clock and power supply decoupling capacitors. it contains a 12-bit successive approximation adc based on a fast-settling voltage-output dac, a high speed comparator and sar, as well as the necessary control logic. the charge balancing comparator used in the ad7880 provides the user with an inherent track- and-hold function. the adc is specified to work with sampling rates up to 66 khz. converter details the ad7880 conversion cycle is initiated on the rising edge of the convst pulse, as shown in the timing diagram of figure 1. the rising edge of the convst pulse places the track/hold amplifier into hold mode. the conversion cycle then takes between 26 and 28 clock periods. the maximum specified con- version time is 12 m s. this corresponds to a conversion cycle time of 28 clock periods with a clkin frequency of 2.5 mhz and also includes internal propagation delays. during conver- sion the busy output will remain low, and the output databus drivers will be three-stated. when a conversion is completed, the busy output will go to a high level, and the result of the conversion can be read by bringing cs and rd low. the track/hold amplifier acquires a 12-bit input signal in 3 m s. the overall throughput time for the ad7880 is equal to the conversion time plus the track/hold acquisition time. for a 2.5 mhz input clock the throughput time is 15 m s. reference input for specified performance, it is recommended that the reference input be tied to v dd . the part, however, will operate with a ref- erence down to 2.5 v though with reduced performance specifi- cations. figure 3 shows a graph of signal-to-noise ratio (snr) versus v ref . v ref must not be allowed to go above v dd by more than 100 mv. 74 72 70 68 66 64 62 60 2345 v ref ?volts snr ? dbs f = 51.2khz s f = 2.525khz in t = 25 c a figure 3. snr vs. v ref analog input the ad7880 has two analog input pins, v ina and v inb . figure 4 shows the input circuitry to the adc sampling comparator. the on-board attenuator network, made up of equal resistors, allows for various input ranges.
ad7880 C6C rev. 0 the ad7880 has two unipolar input ranges, 0 v to 5 v and 0 v to 10 v. figure 5 shows the analog input for the 0 v to 5 v range. the designed code transitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs C3/2 lsbs). the output code is straight binary with 1 lsb = fs/ 4096 = 5 v/ 4096 = 1.22 mv. the same applies for the 0 v to 10 v range, as shown in figure 6, except that the lsb size is bigger. in this case 1 lsb = fs/ 4096 = 10 v/ 4096 = 2.44 mv. the ideal input/output transfer characteristic for both these unipolar ranges is shown in figure 8. 1lsb = fs 4096 output code 0v 111...111 111...110 111...101 111...100 000...011 000...001 000...000 a a a a a a a a a a a a a a 000...010 v input voltage in 1lsb fs ?1lsb + figure 8. ad7880 unipolar transfer characteristic figure 7 shows the ad7880s 5 v bipolar analog input con- figuration. once again the designed code transitions occur mid- way between successive integer lsb values. the output code is straight binary with 1 lsb = fs/ 4096 = 10 v/ 4096 = 2.44 mv . the ideal bipolar input/output transfer characteristic is shown in figure 9. a a a a a a a a a a a a a a fs 2 fs = 10v 1lsb = 4096 fs output code 111...111 111...110 100...101 100...000 011...111 011...110 000...001 000...000 fs + 2 1lsb 0v v input voltage in 1lsb 1lsb + figure 9. ad7880 bipolar transfer characteristic clock input the ad7880 is specified to operate with a 2.5 mhz clock con- nected to the clkin input pin. this pin may be driven directly by cmos or ttl buffers. the mark/space ratio on the clock can vary from 40/60 to 60/40. as the clock frequency is slowed down, it can result in slightly degraded accuracy performance. this is due to leakage effects on the hold capacitor in the inter- nal track-and-hold amplifier. figure 10 is a typical plot of accu- racy versus clock frequency for the adc. 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.5 2.5 3.5 clock frequency ?mhz normalized linearity error figure 10. normalized linearity error vs. clock frequency track/hold amplifier the charge balanced comparator used in the ad7880 for the a/d conversion provides the user with an inherent track/hold function. the track/hold amplifier acquires an input signal to 12-bit accuracy in less than 3 m s. the overall throughput time is equal to the conversion time plus the track/hold amplifier acqui- sition time. for a 2.5 mhz input clock, the throughput time is 15 m s. the operation of the track/hold amplifier is essentially transpar- ent to the user. the track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion, i.e., on the ris- ing edge of convst as shown in figure 1. offset and full-scale adjustment in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the adc. some applications will require that the input signal range match the maximum possible dynamic range of the adc. in such applications, offset and full-scale error will have to be adjusted to zero. the following sections describe suggested offset and full-scale adjustment techniques which rely on adjusting the inherent off- set of the op amp driving the input to the adc as well as tweak- ing an additional external potentiometer as shown in figure 11.
ad7880 rev. 0 C7C + v 1 r1 10 k w v ina agnd ad7880* r2 500 w r3 10 k w r5 10 k w r4 10 k w *additional pins omitted for clarity figure 11. offset and full-scale adjust circuit unipolar adjustments in the case of the 0 v to 5 v unipolar input configuration, unipolar offset error must be adjusted before full-scale error. ad justment is achieved by trimming the offset of the op amp driving the ana- log input of the ad7880. this is done by applying an input voltage of 0.61 mv (1/2 lsb) to v 1 in figure 11 and adjusting the op amp offset voltage until the adc output code flickers between 0000 0000 0000 and 0000 0000 0001. for full-scale adjustment, an input voltage of 4.9982 v (fsC3/2 lsbs) is applied to v 1 and r2 is adjusted until the output code flickers between 1111 1111 1110 and 1111 1111 1111. the same procedure is required for the 0 v to 10 v input con- figuration of figure 6. an input voltage of 1.22 mv (1/2 lsb) is applied to v 1 in figure 11 and the op amps offset voltage is adjusted until the adc output code flickers between 0000 0000 0000 and 0000 0000 0001. for full-scale adjustment, an input voltage of 9.9963 v (fsC3/2 lsbs) is applied to v 1 and r2 is adjusted until the output code flickers between 1111 1111 1110 and 1111 1111 1111. bipolar adjustments bipolar zero and full-scale errors for the bipolar input configura- tion of figure 7 are adjusted in a similar fashion to the unipolar case. again, bipolar zero error must be adjusted before full-scale error. bipolar zero error adjustment is achieved by trimming the offset of the op amp driving the analog input of the ad7880 while the input voltage is 1/2 lsb below ground. this is done by applying an input voltage of C1.22 mv (1/2 lsb) to v 1 in figure 11 and adjusting the op amp offset voltage until the adc output code flickers between 0111 1111 1111 and 1000 0000 0000. for full-scale adjustment, an input voltage of 4.9982 v (fs/2C3/2 lsbs) is applied to v 1 and r2 is adjusted until the output code flickers between 1111 1111 1110 and 1111 1111 1111. dynamic specifications the ad7880 is specified and tested for dynamic performance specifications as well as traditional dc specifications such as integral and differential nonlinearity. the ac specifications are required for signal processing applications such as speech recog- nition, spectrum analysis and high speed modems. these appli- cations require information on the adcs effect on the spectral content of the input signal. hence, the parameters for which the ad7880 is specified include snr, harmonic distortion, inter- modulation distortion and peak harmonics. these terms are dis- cussed in more detail in the following sections. signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. snr is depen- dent upon the number of quantization levels used in the digiti- zation process; the more levels, the smaller the quantization noise. the theoretical signal to noise ratio for a sine wave input is given by: snr = (6.02 n + 1.76) db (1) where n is the number of bits. thus for an ideal 12-bit converter, snr = 74 db. the output spectrum from the adc is evaluated by applying a sine wave signal of very low distortion to the v in input which is sampled at a 66 khz sampling rate. a fast fourier transform (fft) plot is generated from which the snr data can be ob- tained. figure 12 shows a typical 2048 point fft plot of the ad7880 with an input signal of 2.5 khz and a sampling fre- quency of 61 khz. the snr obtained from this graph is 73 db. it should be noted that the harmonics are taken into account when calculating the snr. figure 12. fft plot effective number of bits the formula given in equation 1 relates the snr to the number of bits. rewriting the formula, as in equation 2, it is possible to get a measure of performance expressed in effective number of bits (n). n = snr - 1. 7 6 6.02 (2) the effec tive number of bits for a device can be calculated directly from its measured snr. figure 13 shows a plot of effective number of bits versus input frequency for an ad7880 with a sampling frequency of 61 khz. the effective number of bits typically remains better than 11.5 for frequencies up to 12 khz.
ad7880 C8C rev. 0 12 11.5 11 10.5 10 input frequency ?khz sample frequency = 61khz t = 25 c a 15 30.5 effective number of bits figure 13. effective number of bits vs. frequency total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad7880, thd is defined as: thd = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 (3) where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonic. the thd is also derived from the fft plot of the adc output spectrum. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the second or- der terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). using the ccif standard where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the inter- modulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. in this case, the input consists of two, equal amplitude, low distortion, sine waves. figure 14 shows a typical imd plot for the ad7880. figure 14. imd plot peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor the peak will be a noise peak.
ad7880 rev. 0 C9C microprocessor interfacing the ad7880 high speed bus timing allows direct interfacing to real time digital signal processors, dsps, as well as modern high speed, 16-bit microprocessors. suitable microprocessor inter- faces are shown in figures 15 through 20. ad7880Cadsp-2100 interface figure 15 shows an interface between the ad7880 and the adsp-2100. conversion is initiated using a timer to drive the convst input asynchronously to the microprocessor. this al- lows very accurate control of the sampling instant. when con- version is complete, the ad7880 busy line goes high. an inverter on this busy output drives the irq line low thus pro- viding an interrupt to the adsp-2100 when conversion is com- pleted. the conversion result is then read from the ad7880 into the adsp-2100 with the following instruction: mr0 = dm(adc) where mr0 is the adsp-2100 mr0 register and where adc is the ad7880 address. timer dma0 dma13 dmd15 dmd0 dms en addr decode address bus adsp-2100 (adsp-2101/ adsp-2102) * additional pins omitted for clarity data bus convst cs db11 db0 rd busy ad7880* irqn dmrd (rd) a a figure 15. ad7880Cadsp-2100 (adsp-2101/adsp-2102) interface ad7880-adsp-2101/adsp-2102 interface the interface outlined in figure 15 also forms the basis for an inter face between the ad7880 and the adsp-2101/adsp-2102. the read line of the adsp-2101/adsp-2102 is labeled rd . in this interface, the rd pulse width of the processor can be programmed using the data memory wait state control regis- ter. the instruction used to read a conversion result is as out- lined for the adsp-2100. ad7880-tms32010 interface an interface between the ad7880 and the tms32010 is shown in figure 16. once again the conversion is initiated using an ex- ternal timer and the tms32010 is interrupted when conversion is completed. the following instruction is used to read the con- version result from the ad7880: in d,adc where d is data memory address and where adc is the ad7880 address. pa0 pa2 d15 d0 men addr decode address bus timer data bus convst cs db11 db0 rd ad7880* tms32010 *additional pins omitted for clarity int den en busy a a figure 16. ad7880Ctms32010 interface ad7880Ctms320c25 interface figure 17 shows an interface between the ad7880 and the tms320c25. as with the two previous interfaces, conversion is initiated with a timer, and the processor is interrupted when the conversion sequence is completed. the tms320c25 does not have a separate rd output to drive the ad7880 rd input di- rectly. this has to be generated from the processor strb and r/ w outputs with the addition of some logic gates. the rd sig- nal is or-gated with the msc signal to provide the one wait state required in the read cycle for correct interface timing. conversion results are read from the ad7880 using the follow- ing instruction: in d,adc where d is data memory address and where adc is the ad7880 address. a0 a15 d15 d0 is en addr decode address bus timer data bus convst cs db11 db0 rd ad7880* tms320c25 *additional pins omitted for clarity intn r/w strb msc ready busy a a figure 17. ad7880Ctms320c25 interface some applications may require that the conversion be initiated by the microprocessor rather than an external timer. one option is to decode the ad7880 convst from the address bus so that
ad7880 C10C rev. 0 a write operation starts a conversion. data is read at the end of the conversion sequence as before. figure 19 shows an example of initiating conversion using this method. a similar implemen- tation can be used for dsps. note that for all interfaces, a read operation should not be attempted during conversion. ad7880Cmc68000 interface an interface between the ad7880 and the mc68000 is shown in figure 18. as before, conversion is initiated using an external timer. the ad7880 busy line can be used to interrupt the processor or, alternatively, software delays can ensure that con- version has been completed before a read to the ad7880 is at- tempted. because of the nature of its interrupts, the 68000 requires additional logic (not shown in figure 18) to allow it to be interrupted correctly. for further information on 68000 in- terrupts, consult the 68000 users manual. the mc68000 as and r/ w outputs are used to generate a separate rd input signal for the ad7880. cs is used to drive the 68000 dtack input to allow the processor to execute a normal read operation to the ad7880. the conversion results are read using the following 68000 instruction: move.w adc, d 0 where d 0 is the 68000 d0 register where adc is the ad7880 address a0 a15 d15 d0 addr decode address bus data bus convst cs db11 db0 rd ad7880* mc68000 *additional pins omitted for clarity r/w as en dtack timer a a figure 18. ad7880Cmc68000 interface ad7880C8086 interface figure 19 shows an interface between the ad7880 and the 8086 microprocessor. unlike the previous interface examples, the microprocessor initiates conversion. this is achieved by gat- ing the 8086 wr signal with a decoded address output (differ- ent to the ad7880 cs address). conversion is initiated and the result is read from the ad7880 using the following instruction: mov ax, adc where ax is the 8086 accumulator and where adc is the ad7880 address ad15 ad0 addr decode address bus address/data bus convst cs db11 db0 rd ad7880* 8086 *additional pins omitted for clarity wr rd latch ale a figure 19. ad7880C8086 interface ad7880C6809 interface the ad7880 can also interface quite easily with 8-bit micro- processors. the 12-bit parallel data output from the ad7880 can be read into the microprocessor as an 8+4 byte structure. figure 20 shows an interface to the mc6809 8-bit microproces- sor. as in previous cases, conversion is initiated using an exter- nal timer. at the end of conversion, busy triggers a one-shot which drives the irq interrupt input of the microprocessor. a double read is then performed to two unique addresses. the first read fetches the lower 8 bits (db0Cdb7) and loads the 74hc374 latch with the upper 4 bits (db8Cdb11). the sec- ond read fetches these upper 4 bits. a0 a15 d7 d0 addr decode address bus timer data bus convst cs db7 db0 rd ad7880* mc6809 *additional pins omitted for clarity r/w irq e busy a a one shot q3 q0 clk d3 d0 74hc374 oe db8 db11 a figure 20. ad7880C6809 interface
ad7880 rev. 0 C11C v+ + c1 10? c2 0.1? ic1 analog input v+ v ab v ab lk2 lk3 to adc lk1 skt1 a a a c3 10? c4 0.1? a a a v+ v dd figure 21. analog input buffering when it is required to drive the ad7880 with the 0 v to 10 v input range, an external supply must be connected to v+ (see figure 21). in bipolar operation, positive and negative supplies must be connected to v+ and vC. the ad711 is a general purpose op amp which could be used to drive the analog input of the ad7880. power-down control (mode input) the ad7880 is designed for systems which need to have mini- mum power consumption. this includes such applications as hand held, portable battery powered systems and remote moni- toring systems. as well as consuming minimum power under normal operating conditions, typically 20 mw, the ad7880 can be put into a power-down or sleep mode when not required to convert signals. when in this power-down mode, the ad7880 consumes approximately 2 mw of power. the ad7880 is powered down by bringing the mode input pin to a logic low in conjunction with keeping the rd input control high. the ad7880 will remain in the power-down mode until mode is brought to a logic high again. the mode input should be driven with cd4000 or hcmos logic levels. it is recommended that one dummy conversion be imple- mented before reading conversion data from the ad7880 after it has been in the power-down mode. this is required to reset all internal logic and control circuitry. in a remote monitoring system where, say, 10 conversions are required to be taken with a sampling interval of 1 second, an additional 11th conversion must be carried out. figure 22 gives a plot of power consumption 01 2 aa time ?secs power consumption ?mw 20 2 converting power-down converting power-down aaa a a a a a a aaa aaaaa aaa a a a a a a aaa aaaaaa 1.65 x 10 4 figure 22. power consumption for normal operation and power-down operation vs. time application hints good printed circuit board (pcb) layout is as important as the circuit design itself in achieving high speed a/d performance. the ad7880s comparator is required to make bit decisions on an lsb size of 1.22 mv. to achieve this, the designer must be conscious of noise both in the adc itself and in the preceding analog circuitry. switching mode power supplies are not recom- mended, as the switching spikes will feed through to the com- parator causing noisy code transitions. other causes of concern are ground loops and digital feedthrough from microprocessors. these are factors which influence any adc, and a proper pcb layout which minimizes these effects is essential for best performance. layout hints ensure that the layout for the printed circuit board has the digi- tal and analog signal lines separated as much as possible. take care not to run digital tracks alongside analog signal tracks. guard (screen) the analog input with agnd. establish a single point analog ground (star ground) separate from the logic system ground at the ad7880 agnd pin or as close as possible to the ad7880. connect all other grounds and the ad7880 dgnd to this single analog ground point. do not connect any other digital grounds to this analog ground point. low impedance analog and digital power supply common re- turns are essential to low noise operation of the adc, so make the foil width for these tracks as wide as possible. the use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise. the circuit layout of fig- ures 26 and 27 have both analog and digital ground planes which are kept separated and only joined together at the ad7880 agnd pin. noise keep the input signal leads to v in and signal return leads from agnd as short as possible to minimize input noise coupling. in applications where this is not possible, use a shielded cable be- tween the source and the adc. reduce the ground circuit im- pedance as much as possible since any potential difference in grounds between the signal source and the adc appears as an error voltage in series with the input signal. analog input buffering to achieve specified performance, it is recommended that the analog input (v ina , v inb ) be driven from a low impedance source. this necessitates the use of an input buffer amplifier. the choice of op amp will be a function of the particular appli- cation and the desired analog input range. the data acquisition circuit, described in this data sheet allows for various op amp configurations. figure 21 shows the analog input buffer circuit. the options available to drive the supply of the op amp are: single +5 v (derived from pcb 5 v supply) dual supply (externally supplied to v+ and vC) 5 v, 12 v or 15 v the simplest configuration is the 0 v to 5 v range of figure 5. a single supply 5 v op amp is recommended for such an imple- mentation. this will allow for operation of the ad7880 in the 0 v to 5 v unipolar range without supplying an external supply to v+ and vC. the 5 v supply is derived from the systems +5 v v dd supply.
ad7880 C12C rev. 0 as a function of time for such operation. the total conversion time for each cycle is 11 15 m s (where 15 m s is the time taken for a single conversion) corresponding to 1.65 10 C4 secs. hence: average power = power converting + power power-down = {20 mw (1.65 10 C4 )/(10)} + {2 mw (9.9998)/(10)} = 2.029 mw ad7880 data acquisition layout figure 24 shows the ad7880 in a data acquisition circuit. the corresponding printed circuit board (pcb) layout and silkscreen are shown in figures 25 to 27. the only additional component required for a full data acquisi- tion system is an antialiasing filter. there is a component grid provided near the analog input on the pcb which may be used for such a filter or any other input conditioning circuitry. to fa- cilitate this option there is a shorting link (labeled lk1 on the pcb) on the analog input track. with lk1 in place, the analog input connects to the buffer amplifier driving the ad7880. with lk1 removed, a wire link is needed to connect the analog input to the pcb component grid. interface connections the data acquisition board contains a parallel connection port labeled skt4. this is a 26-contact idc connector and pro- vides for direct microprocessor connection to the board. this connector, the pinout of which is shown in figure 23, contains all data, control and status signals of the ad7880 (with the ex- ception of the convst and the clkin inputs both of which are provided via skt2 and skt3 respectively). it also contains decoded r/ w and strb inputs which are necessary for inter- facing to many microprocessors including the tms320c25 and the motorola 68000 series. link lk7 selects rd directly or al- ternatively, the decoded version. note that the ad7880 cs in- put must be decoded prior to the ad7880 evaluation board. skt1, skt2 and skt3 are three sub-miniature connectors (smc) which provide input connections for the analog input, the convst input and the clkin input. three different in- put ranges can be accepted by the ad7880 each of which is configured by selecting shorting plug options a, b or c of lk4. position a corresponds to the 0 v to 5 v unipolar configuration of figure 5, position b corresponds to the bipolar 5 v configu- ration of figure 7 and position c allows for a 0 v to +10 v uni- polar range as shown in figure 6. power supply connections the pcb requires a single +5 v power supply (labeled v dd ). good decoupling allows this supply to drive the ad7880 v dd which also drives the v ref input as well as the op amp power supply. in circumstances where bipolar 5 v or a unipolar 0 v to 10 v input ranges are required, provision has been allowed for the connection of separate op amp power supplies ( 15 v, 12 v, 5 v, etc.) to v+ and vC. lk2 and lk3 shorting links allow for the selection of user defined op amp power supplies or the on-board single +5 v supply. link options there are seven link options which must be set before using the board. these are outlined below: lk1 connects the analog input to a buffer amplifier. the analog input may also be connected to a component grid for signal conditioning. lk2, lk3 allows for various op amp power supplies to be used to drive the input buffer of the ad7880. ex- ternal supplies may be connected to v+ and vC. alternatively, the ad7880s +5 v system supply and agnd can be selected to drive a single supply op amp. lk4 configures the various analog input ranges, 0 v to 5 v, 0 v to 10 v or 5 v. lk5 selects reference input to v ref of ad7880. nor- mally connected to v dd . an external reference could also be wired in. lk6 selects power-down or sleep mode. the shorting plug is connected to v dd for normal operation. lk7 connects the ad7880 rd input directly to the rd input of skt4 or to a decoded strb and r/ w input. this shorting plug setting depends on the microprocessor, e.g., the tms320c25 requires a decoded rd signal. db10 db8 db6 db4 db2 db0 gnd r/w rd cs 1 3 5 7 9 13 15 17 19 25 23 21 11 n/c 2 4 6 8 10 14 16 18 20 26 24 22 12 db11 db9 db7 db5 db3 db1 gnd strb busy n/c n/c n/c 5v + 5v + busy figure 23. skt4, idc connector pinout component list ic1 op amp* ic2 ad7880 analog-to-digital converter ic3 74hc00 quad nand gate c1, c3, c5 10 m f capacitors c2, c4, c6, c7 0.1 m f capacitors r1, r2 10 k w pull-up resistors lk1, lk2, lk3 shorting links lk4, lk5, lk6 lk7 skt1, skt2, skt3 sub-miniature connectors vendor no: sealectro 50-051-0000 (socket) vendor no: sealectro 50-007-0000 (plug) skt4 26-contact (2 row) idc connector note *see analog input buffering section. .
ad7880 rev. 0 C13C figure 24. data acquisition circuit using the ad7880 figure 25. pcb silkscreen for figure 24
ad7880 C14C rev. 0 figure 26. pcb component side layout for figure 24 figure 27. pcb solder side layout for figure 24
ad7880 rev. 0 C15C outline dimensions dimensions shown in inches and (mm). 24-lead plastic dip (n-24) 24 112 13 1.228 (31.19) 1.226 (31.14) 0.260 0.001 (6.61 0.03) pin 1 seating plane 0.02 (0.5) 0.016 (0.41) 0.130 (3.30) 0.128 (3.25) 0.07 (1.78) 0.05 (1.27) 0.32 (8.128) 0.30 (7.62) 0.011 (0.28) 0.009 (0.23) 15 0 0.11 (2.79) 0.09 (2.28) notes: 1. lead no. 1 identified by dot or notch. 2. plastic leads will be either solder dipped or tin lead plated in accordance with mil-m-38510 requirements. 24-lead cerdip (q-24) 24 1 12 13 0.295 (7.493) max seating plane 0.021 (0.533) 0.015 (0.381) typ 0.225 (5.715) max 1.290 (32.77) max 0.125 (3.175) min 0.110 (2.794) 0.009 (2.286) typ 0.070 (1.778) 0.020 (0.508) 0.065 (1.651) 0.055 (1.397) 15 0 0.320 (8.128) 0.291 (7.4) 0.012 (0.305) 0.008 (0.203) 0.180 (4.572) max 1. lead no. 1 identified by dot or notch. 2. cerdip leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements. 24-lead soic (r-24) 24 13 12 1 0.614 (15.6) 0.598 (15.2) pin 1 0.012 (0.3) 0.004 (0.1) 0.019 (0.49) 0.014 (0.35) 0.104 (2.65) 0.093 (2.35) 0.05 (1.27) bsc 0.013 (0.32) 0.009 (0.23) 0.05 (1.27) 0.016 (0.40) 8 0 0.03 (0.75) 0.01 (0.25) 0.419 (10.65) 0.394 (10.00) 0.299 (7.6) 0.291 (7.4)
c1414C10C6/90 printed in u.s.a. C16C

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